An insulated-gate field-effect transistor (FET) made from a body of monocrystalline silicon according to state-of-the-art semiconductor processing techniques usually consists of a conductively doped polycrystalline silicon (polysilicon) gate electrode, a thin gate dielectric lying under the gate electrode, and a pair of source/drain (S/D) regions formed in the semiconductor body. The S/D regions are separated from each other by a channel region that lies below the gate dielectric.
The S/D regions are typically created by ion implantation in which the gate electrode is used as a shield to prevent implantation into the channel. At the end of the implantation, the sides of the gate electrode are in substantial vertical alignment with the inside boundaries of the S/D regions. However, lateral diffusion of the implanted dopant during subsequent heating steps causes the gate electrode to partially overlap the S/D regions in the final FET. The overlap causes a loss in effective channel length and a loss in FET speed.
One technique for controlling the vertical alignment is to form insulating spacers along the sidewalls of the gate electrode before performing the ion implantation to define the S/D regions. The sidewall spacers then act as a further implantation shield during the S/D implantation. This increases the initial lateral separation between the S/D regions, thereby substantially reducing undesirable overlap of the gate electrode to the S/D regions.
In U.S. Pat. No. 4,420,872, Solo (de Zaldivar) creates sidewall spacers by thermally oxidizing side portions of a patterned polysilicon layer formed on the gate dielectric. The oxidation is done at 1050.degree. C. A layer of silicon nitride lying on the polysilicon layer largely prevents the underlying polysilicon at the intended location for the gate electrode from being oxidized.
Later in the fabrication process, Solo etches contact openings through silicon dioxide along the upper surfaces of the S/D regions. The spacers and nitride layer protect the gate electrode. Although Solo actually performs the etch using a photoresist mask, the S/D contact openings are self-aligned in that the boundaries of the openings nearest the gate electrode are determined by the spacers rather than the photoresist pattern. The self-alignment leads to a relatively compact FET.
A disadvantage of Solo is that some of the polysilicon that forms the bottom surface of the gate electrode near its sidewalls is oxidized during spacer formation. This phenomenon is termed "gate dielectric encroachment" because the thickness of the gate dielectric becomes significantly greater at the sides than in the middle. The encroachment reduces the effective area of the gate electrode. Also, the S/D regions must be driven laterally in further below the gate dielectric. This usually leads to a performance degradation because the S/D regions go deeper into the semiconductor body at the same time.
Gate dielectric encroachment is substantially avoided when the sidewall spacers are formed by a combination of oxide deposition and anisotropic etching. Ogura et al, "Elimination of Hot Electron Gate Current by the Lightly Doped Drain-Source Structure," IEEE IEDM Tech. Dig., 7-9 Dec. 1981, pp. 651-654, employ this process in fabricating a so-called lightly doped drain (LDD) FET. In material part, Ogura et al start by forming a structure in which a patterned cover layer of silicon dioxide lies on a similarly patterned doped polysilicon layer (destined to become the gate electrode). The polysilicon layer lies on a dielectric layer located along the upper surface of a P-type region of a monocrystalline silicon body. Using the two patterned layers as an implantation shield, the LDD part of the FET is created by implanting an N-type dopant at a low dosage into the P-type region.
A layer of silicon dioxide is then deposited conformally on the upper surface of the structure. Using an anisotropic etchant, largely all of the conformal layer is removed except for small spacer portions that adjoin the sidewalls of the polysilicon layer. Due to the nature of the etching process, each of the sidewall spacers is thicker at the bottom than at the top.
The main portions of the S/D regions are formed by implanting an N-type dopant into the P-type region using the spacer portions and the patterned layers as an implantation mask. An annealing heat treatment is then performed to repair lattice damage and activate the implanted species. Parts of the polysilicon layer and the P-type region are oxidized along their upper surface during the heat treatment. The remaining polysilicon forms the gate electrode.
Because the same material--i.e., silicon dioxide--lies on both the gate electrode and the S/D regions in Ogura et al, it is extremely difficult to etch self-aligned contact openings down to the S/D regions without exposing the gate electrode at the same time. A critical photoresist mask must be utilized to define the S/D contact openings. This increases the FET die area.